Definition of high speed PCB Design and its guidelines
In this article, we are going to discuss about the high speed PCB Design and its guidelines
A circuit is considered high-speed “when the rise/fall time of a signal is fast enough that the signal may be change from one logic state to the other in less time than it takes for it to travel the length of the conductor and back. Generally one From this definition it is obvious that two critical factors determine if a circuit is operating at a high-speed: the switching time of the device(s) on the circuit & the length of the circuit. It is important to note that the “clock speed” of the circuit does not determine whether it is operating in the high-speed domain.
Use 45° angle or smooth curves, in order to minimize signal reflection. Sharp corners have a high field strength.
Avoid stubs or tees, vias, sharp 90° turns, all of which cause impedance discontinuities.
Minimize the number of signals that cross PWR domains. Each PWR plane should have HF decoupling caps between the planes to provide a return path for signals that cross from one domain to another.
Consider using buried capacitance pwr or gnd planes. This technology reduces HF bypass capacitor count. Unfortunately, this technology is expensive & of limited availability. The added cost can be partially offset by savings in HF capacitors.
Use all available pwr & gnd pins. This may seem obvious but it is not always done. Some schematic symbols define VCC & GND connections implicitly so they are not visible on the schematic. Therefore, it may not be apparent that some are missing. It is preferred to specify pwr & gnd explicitly on the schematic.
Consider board stackup order. It is preferable to have the gnd plane as close as possible to the components. Place the VCC plane towards the bottom side of the board.
Border the PCB with chassis gnd or place the VCC plane back from the edge of the board by three times the distance between planes.
Microstrip should only be used for short traces, traces with slow rise time signals & where driver & load are isolated from clock. (In practice, Microstrip is used for all signals &clks)
Stripline should be used when possible. It is especially desirable for clocks. (In practice it is rarely used on 4-layer boards.)
Keep clock chips or clock lines away from the edges of the board.
Minimize the trace length of clock lines.
Keep clocks away from I/O lines and connectors.
Avoid running traces under crystals, clock chips, or other “hot” circuits. (Hot in the EMI sense means noisy, HF/high energy, not high temp.) A good way to ensure this is to put a cross-hatched gnd plane on the surface under the oscillator/clock chip, which prevents crosstalk between the clock & signals.
To minimize crosstalk, use a trace spacing-to-height ratio greater than 2. Unfortunately, this is seldom practical due to space constraints. Usually, the designer must settle for approximately 1:1. Good signal integrity tools are important in this context.
Put line driver & receiver near the port they drive. Put filters as close to the connector as possible to prevent unwanted signals coupling into the output of the filter.
Use ferrites or LP filters on signals that go to an external cable.
Route diffl pairs together, so their lengths are matched & any common-mode noise is cancelled out.