DESIGN RULES FOR ANALOG AND DIGITAL PCB DESIGN

In this article we are discussing about WHAT ARE THE DESIGN RULES FOR ANALOG AND DIGITAL PCB DESIGN?

 

DESIGN RULES FOR ANALOG AND DIGITAL PCB DESIGN


High frequency analogue signals

·         Keep HF trace lengths as short as possible to reduce emitted radiation & pick up points.

·         Route HF traces away from sensitive signal lines to avoid cross coupling. Use GND ‘guard’ traces to Provide screening for reducing HF radiation.

·         Avoid using sharp corners-an important factor at RF, since 90° corners in traces act as points of high Electrical field strength & constitute an impedance discontinuity & hence a possible source of radiation.

·         This is generally only applicable when the frequency is in excess of 100MHz.

·         If possible, route traces away from the microprocessor instead of underneath it.

·         Keep clock chips or clock lines away from the edges of the board.

·         Place the clock circuit in the center of the board or near the connector if the clock goes off the board.

 

High frequency Digital signals

·         Use capacitance effects of guard traces to increase logic rise & fall times & hence reduce radiatedBandwidth if possible.

·         Try to avoid using sharp corners, to reduce possible radiation.

·         Keep HF trace lengths like clock lines & busses as short as possible to reduce emitted radiation.

·         Route High Frequency digital lines away from sensitive analog signal lines to avoid cross coupling & noise on analog lines. Keeping Noise Close to the Chip noise of the clock errors when the pin is static. Noise on the pins is coupled internal to the device through many paths that can change according to the pin function changes. Like that  the input pin in a keyboard scan has capacitive coupled noise from both the substrate & the PWR rails. Also, because it is hi-z, any ambient fields couple efficiently. If the key is pushed, the pin has a new set of noise sources because the signal line’s impedance has changed. Thus, it is difficult to effectively develop a matrix of all possibilities; therefore, the following is recommended:

·         Put a 50 –100- W resistor in series with every o/p pin & 35W–50W resistor on every i/p pin. If the Hardware design calls for higher series resistance, use that value. Higher resistances are better for o/ps, but usually don’t improve characteristics of inputs. Put the resistor as close as possible to the microcomputer, overlapping the microcomputer GND if possible.

·         Bypass any pin on the microcomputer to GND using a 1000-pF capacitor, provided the edge rate Used for the signal line is not faster than 100 ns. On o/ps & pins that the system uses for both I/O, GND for the capacitor should be the microcomputer GND. The second end of the capacitor should be close to the receiver side, not the microcomputer side, of the series resistor.

·         When pins used for input only, place the capacitor inside, on the microcomputer side, of the resistor to reduce the loop area. Then, HF originating in the microcomputer on the pin see less impedance to GND through the capacitor than through the resistor.

·         Reset & interrupt are special functions, thus care must be taken not to reduce functionality.

·         Don’t apply any of the above remedies to oscillator pins. If proper spacing between the oscillator Components & other unrelated components & traces is maintained, there shouldn’t be a need for Oscillator signal conditioning.

·         Unused pins should be configured as inputs & tied directly to the microcomputer GND.

·         Signals leaving the enclosure.

·         Signals routing the PCB to other boards inside the enclosure

·         Signals staying on the PCB with high-impedance loads (i.e., driving another MOS input or open circuit)

·         Pins of parallel Input and output port designed to support high speed data transfer, e.g., between the microcomputer & an external memory, need filtering over the remaining I/O pins, because of their faster rise & fall times. When the design is complete & first prototypes are built, an hour or 2 in the screen room removing each of the filtering components one at a time, identifies which are or are not needed to get the desired EMI level.

 

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