HOW TO REDUCE NOISE FROM POWER SUPPLY PCB AND PCB DESIGN OF CLOCK?
In this tutorial we are going to learn about
noise reduction circuit, consisting of a ferrite bead, filter capacitor, & bypass capacitors for each system VCC, should be implemented. A summary of each component of the power supply noise reduction circuit follows:
It is used to block HF noise from the . FBs prevents the noise generated by the clk generator from reaching the main PWR supply plane. A minimum of 1.7 Henries is recommended, however, the bigger the FB, the better the noise reduction. Available board space must be considered when choosing the FB’s value because if provides noise isolation only & doesn’t enhance or degrade the performance of a clock generator. Use only those FBs that can provide the rated DC current to the VCC island without saturating. In addition, the DC impedance of the FB must be as low as possible, preferably between 0-5 ?. At the clock frequency, the impedance of the FB must be relatively high, typically greater than 50? under loaded conditions with DC current flowing through it. The FB will then present a large impedance at the clock frequency, and will prevent noise arising from clock harmonics spreading around the PCB.
Each clk generator VDD pin should have a 0.1μF cap to GND for elimination of crosstalk between clk o/p frequencies. These caps must be placed as close to the device pins as possible on the same side of the clk generator chip, preferably within 0.25 inches of the pins. For the best performance, the use of high-quality, monolithic, ceramic, SM caps.
: A 22μF tantalum cap is used to eliminate LF noise from the PWR supply. This capacitor prevents Power supply droop when the clk generator is switching all outputs simultaneously with maximum capacitive load. Destabilization of the PWR supply will result in increased jitter of the clk outputs. Place this cap on the clk-generator side of the ferrite be as close to it a physically possible.
· If there using Op Amps in the design, terminate unused op-amps in dual and quad packs by grounding the positive input and connecting the – input to the output.
· Filter all signals leaving a noisy environment & filter all signals entering the board
· Place Input & output drivers near where they leave the board.
· Place the crystals flush to board and ground them.
· Place the clock at the center of the board, however, if the clock goes off the board, place the clock near the connector.
· Divide the circuits on the board based on their frequency & current switching levels.
· Separate noisy and quiet leads.
· Avoid using snake angle routing; clock traces should be as straight as possible.
· Avoid routing multiple signal layers for clock signals.
· Avoid using vias in the clock TM line, since vias can contribute impedance change & reflection.
· Route the clock trace on the micro strip (preferably top layer) to minimize the use of vias & delays, since air is the dielectric material. Air must have the lowest dielectric constant Er = 1
· Place a gnd plane next to the outer layer to minimize noise. If using the inner layer for routing the clk trace, sandwich the layer by gnd planes to reduce delay.
· First Separate digital and analog lines then route the signals away from each other.
· Clk & digital signal lines must be placed as far away as analog i/p & voltage reference pins.
· Clock circuits must be placed away from I/O cables.
· The length of sensitive leads such as decoupling cap must be of short.
· Don’t open all power and ground pins of an IC. Try to use all power and ground pins of an IC.
· Place the ground lead between low level signal leads and noisy leads in the same connector like a ribbon cable.
· Keep high-speed lines short and direct.
· Avoid running traces under the crystal.
· Sensitive traces should not be run in parallel with high current, fast switching signals.
· Critical traces should have wide trace width and must be guarded with a GND on each side of the trace.